With static random access memory (SRAM), stored data is retained as long as the memory is powered. In conventional 6T SRAM designs, each SRAM cell includes six transistors—four for storing data while the other two serve as access transistors.
The incorporation of six transistors per cell is, however, costly in terms of chip density. 6T SRAM designs are not compatible with the scaled technology currently being explored. As such, 4T SRAM cell designs have been proposed for stand-alone SRAM devices.
However, extremely leaky p-channel field effect transistors (PFETs) are needed in the current 4T SRAM designs to retain the cell node. See, for example, Noda et al., “A Loadless CMOS Four-Transistor SRAM Cell in a 0.18-um Logic Technology,” IEEE Transactions on Electron Devices, Vol. 48, No. 12 (December 2001). As a result, standby cells can undesirably overwhelm the READ signal
Therefore, improved 4T SRAM designs would be desirable.